The demand for higher data rates in electronic circuits is permanent. If the data rate of a signal is higher than the bandwidth of a channel used by the signal, the signal integrity can degrade, generating unwanted phenomena like reduced-eye opening, jitter, inter-symbol interference, etc.
Such limitations due to a channel can be overcome with an equalizer located between a signal source and the channel. For example, when a data source sends a signal to an equalizer, the equalizer can introduce predistortion in the signal such that the signal output from a channel located after the equalizer is essentially unchanged with respect to the signal output from the data source. In other words, the equalizer acts as a filter that implements the inverse characteristic of the channel so that the usable frequency range is extended for high data rate signals. At high frequency, the equalizer may be a Feed-Forward Equalizer (FFE), or, more specifically, a travelling-wave type FFE.
A problem may occur when the FFE or its functionality need to be tested, for example, when the gain of variable gain amplifiers of the FFE have to be determined, during the development phase of a product including a FFE, or during the tests following the circuit production. In a practical system, the FFE may be soldered between other circuit components on a Printed Circuit Board (PCB). As such, it may not be possible to test the FFE individually without disconnecting the FFE from the PCB or without inserting test multiplexers that degrade the signal quality, especially at high frequencies.
The FFE may also be integrated in the same integrated circuit as other electronic building blocks, and therefore it becomes difficult to test the FFE individually. Adding test ports next to the conventional input and output ports generally disturbs high-frequency signals because extra circuitry is required on the high speed data path to allow either an internal data signal or an external test signal to be connected to the FFE input and output. This extra circuitry introduces extra power consumption and additional parasitics that degrade the signal quality and bandwidth of the data path.
This problem is acknowledge in the paper “Testable Design for Advanced Serial-Link Transceivers,” where Mitchell Lin and Kwang-Ting Cheng describe a design to characterize a Decision-Feedback Equalizer (DFE). This design modifies the conventional DFE topology by using flip-flops.